1. Field of the Invention
The present invention relates to a semiconductor unit, and particularly to a semiconductor unit containing a multilayer printed-circuit board.
As computer systems are demanded to have a high-speed processing capabilities, operation frequencies used in semiconductor units constituting the computer systems have increased, by tens MHz through hundreds MHz, for example.
Such high operation frequencies may cause the relevant semiconductor units to emit noise occurring due to inductance formed by power supply circuits included in the semiconductor units. Such noise occurs as current amounts flowing in the semiconductor units transitionally vary as a result of transistors' switching operations. Such noise, which may adversely affect operations in the relevant computer systems, should be reduced to the utmost.
Use of a multilayer printed-circuit board, such as that shown in FIG. 2 described later, in a semiconductor unit is a method to reduce such noise. In such a multilayer printed-circuit board, a grounding layer is included, the grounding layer being a continuous-plane conductor (an entire area of the layer is a grounding conductor). Increasing an area at which grounding current effectively flows in the entire area of the grounding layer reduces inductance formed by a relevant power-supply circuit. Thus, increasing of such an area of which grounding current effectively flows in the entire area of such a grounding layer is effective to reduce relevant noise.
2. Related Art
With reference to FIGS. 1, 2 and 3, a land-grid-array (LGA) type printed-circuit board package 10 in the related art will now be described. FIG. 1 shows a bottom surface of the package 10 and FIG. 2 shows a side-elevational sectional view of the package 10 taken along a line II--II shown in FIG. 1. FIG. 2 shows the package so that the bottom surface of the package is located at a top of the figure for the sake of description. The package 10 will be mounted on a substrate via a socket 30 shown in FIG. 2 so that electric circuits contained in the package 10 are connected with electric circuits formed on the substrate. The package 10 packing a semiconductor device 12 therein includes a heat spreader 11, a multilayer printed-circuit board 13 and a lid 14.
The printed-circuit board 13 includes conductor layers consisting of two continuous-plane-conductor power supply layers 15, three continuous-plane-conductor grounding layers 16, and two signal circuit pattern layers 17, as shown in FIG. 2. An insulator layer is provided in each space present between adjacent conductor layers so as to electrically insulate the conductor layers from one another. The insulator layers may be made of ceramic or the like. Power supply through holes 18, grounding through holes 19 and signal through holes 20 are formed in the printed-circuit board 13, as shown in FIG. 2. Each of the through holes 18, 19 and 20 has conductor metal plated on a wall thereof so as to form a connecting conductor for connecting conductor patterns formed on relevant layers of the layers 15, 16 and 17 as a result of the connecting conductor coming into contact with the conductor patterns, the through hole being bored substantially perpendicular to the layers. An opening 21 is formed at a middle of the package 10 as shown in FIG. 1. The signal circuit pattern layers 17 have inner conductor patterns 23 thereon at peripheries of the opening 21 as shown in FIG. 2, the inner conductor patterns 23 being exposed as inner edges of the layers form steps 22 as shown in FIG. 2. Electric circuits contained in the semiconductor device 12 are connected with the inner conductor patterns 23 via bonding wires 28.
The printed-circuit board 13 further has power supply land contacts 25, grounding land contacts 26, signal land contacts 27 on the bottom surface 24 of the printed-circuit board 13. Each contact of the above land contacts 25, 26, and 27 has a plane surface, with which a projecting end of a relevant pin 31 comes into contact, as shown in FIG. 2. As shown in FIGS. 1 and 2, each land contact of the land contacts 25, 26 and 27 is located beside an open end of a relevant through hole of the above through holes 18, 19 and 20, the lands being connected with the conductor metal, acting as the connecting conductor, provided on the walls of the through holes 18, 19 and 20, respectively, as shown in FIG. 2. These contacts 25, 26 and 27 will come into contact with the relevant pins 31 projecting from the above-mentioned socket 30 as shown in FIG. 2 so as to establish electrical contact between the substrate having the socket 30 provided thereon and the conductor patterns in the forms of the layers 15, 16 and 17 via the connecting conductors provided in the through holes 18, 19 and 20 and the contacts 25, 26 and 27. Thus, the electrical circuits contained in the semiconductor device 12 are connected with the electrical circuits contained in the substrate.
Further, as shown in FIG. 1, the pairs of the land contacts and respective through-hole open ends are staggeringly arranged on the bottom surface 24. The pairs are arranged in an area surrounding the lid 14 covering a top (in FIG. 2) of the opening 21 as shown in the figure. For the sake of clear description, indication of the pairs of the power supply and signal land contacts 25 and 27 and through holes 18 and 20 is partially omitted in FIG. 1. In FIG. 1, the hatched pairs of the land contacts and through-hole open-ends correspond to the grounding land contacts 26 and the grounding through holes 19. As shown in FIG. 1. the pairs of the grounding land contacts 26 and through holes 19 are distributed so that a density of the above pairs is approximately uniform over an entire arrangement of the pairs including the land contacts 25, 26 and 27 and the open ends of the through holes 18, 19 and 20. Relevant noise is attempted to be reduced by arranging the grounding land contacts 26 and through holes 19 in such a uniform distribution manner in the related art.
However, the arrangement of grounding land contacts and connecting conductors provided in the through holes such as that described above and shown in FIG. 1 provides an area 40 in which grounding current effectively flows as shown in FIG. 3. The above grounding-current effective flowing area 40 is a cross-hatched area in FIG. 3. As shown in FIG. 3, only a narrow area near a center of the package 10 is used for the grounding current to flow in each grounding layer 16 although each grounding layer 16 consists of a continuous-plane conductor such as that described above. Such a narrow grounding-current effective flowing area 40 may not sufficiently reduce inductance formed by power supply circuits contained in the package 10. In particular, if a semiconductor unit such as the package 10 uses high operating frequencies of tens MHz through hundreds MHz, such a narrow grounding-current effective flowing area 40 may not sufficiently reduce noise occurring due to the inductance.